The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Digital data can be communicated through various channels. Examples of channels include magnetic storage media, optical storage media, wired communication links, wireless communication links, and the like. During transmission and/or recording onto the media, the integrity and recoverability of the data can be enhanced by various codes. The codes can be applied in combination and provide functions such as error correction, DC bias limiting, channel effect estimation, and the like.
Referring now to FIG. 1, a functional block diagram is shown of a coding system 10 in accordance with the prior art. Coding system 10 includes an error correcting code (ECC) encoder module 12 that receives data and encodes it with an ECC, such as a Reed-Solomon (RS) code. A constrained encoder module 14 receives the ECC encoded data and further encodes it with a constrained code, such as a run-length limited (RLL) code and/or a DC-free code. A channel 16 receives the encoded data from constrained encoder module 14. A constrained decoder module 18 receives the encoded data from channel 16 and decodes the constrained code. Constrained decoder module 18 communicates the data to an ECC decoder module 20. ECC decoder module 20 restores the original data.
Referring now to FIG. 2, a functional block diagram is shown of an alternative coding system 10′. Coding system 10′ is similar to coding system 10 of FIG. 1, except constrained encoder module 14 is upstream of ECC encoder module 12 and ECC decoder module 20 is upstream of constrained decoder module 18. The order of ECC and constrained code encoders and decoders are reversed from FIG. 1 to avoid error propagation through channel 16 and to improve a rate of the constrained code.
In coding system 10′, ECC encoder module 12 may destroy the constrained property, such as a RLL and/or DC-bias limit, of the constrained code. A second constrained encoder module (shown in FIG. 6) may be needed to encode ECC parity bits that are generated by ECC encoder module 12. More discussion on such a scheme can be found in J. L. Fan and A. R. Calderbank, “A Modified Concatenated Coding Scheme, with Applications to Magnetic Data Storage,” IEEE Transactions on Information Theory, vol. 44, no. 4, pp. 1565-1574, July 1998, which is hereby incorporated by reference in its entirety.
Referring now to FIG. 3, a functional block diagram is shown of a coding system 30 that employs an inner code in addition to the ECC and constrained code. The inner code may improve the data integrity through channel 16. The inner code can take advantage of soft information such as probability, reliability metric, log likelihood ratio, and the like, for decoding the data from channel 16. An inner encoder module 32 applies the inner code to the data stream just prior to reaching channel 16. An inner decoder module 34 receives encoded data from channel 16 and decodes the inner code based on soft information that is associated with properties of channel 16.
Examples of inner codes include single and multi-parity codes, turbo codes, low-density parity check codes, tensor-product codes, and the like. Single and multi-parity codes are discussed in T. Conway, “A New Target Response with Parity Coding for High Density Magnetic Recording Channels,” IEEE Transactions on Magnetics, vol. 34, no. 4, pp. 2382-2386, July 1998 and R. D. Cideciyan, J. D. Coker, E. Eleftheriou, and R. L. Galbraith, “Noise Predictive Maximum Likelihood Detection Combined with Parity-Based Post-Processing,” IEEE Transactions on Magnetics, vol. 37, no. 2, pp. 714-720, March 2001, and W. Feng, A. Vityaev, G. Burd, and N. Nazari, “On the Performance of Parity Codes in Magnetic Recording Systems,” Proceedings of IEEE GLOBECOM '00, pp. 1877-1881, November 2000, which are hereby incorporated by reference in their entirety. Turbo codes are discussed in W. E. Ryan, “Performance of High Rate Turbo Codes on a PR4-Equalized Magnetic Recording Channel,” Proceedings of IEEE ICC '98, pp. 947-951, June 1998, which is hereby incorporated by reference in its entirety. Low-density parity-check codes are discussed in T. Morita, M. Ohta, and T. Sugawara, “Efficiency of Short LDPC Codes Combined with Long Reed-Solomon Codes for Magnetic Recording Channels,” IEEE Transactions on Magnetics, vol. 40, no. 4, pp. 3078-3080, July 2004, which is hereby incorporated by reference in its entirety. Tensor-product codes are discussed in P. Chaichanavong and P. H. Siegel, “Tensor-Product Parity Code for Magnetic Recording,” IEEE Transactions on Magnetics, vol. 42, no. 2, pp. 350-352, February 2006, and J. Xu, P. Chaichanavong, Z. Wu, and G. Burd, “Tensor Product Codes Containing an Iterative Code,” U.S. Patent Application (MP0767)., which are hereby incorporated by reference in their entirety.
Referring now to FIG. 4, the data stream is shown at various points in the transmitter portion of coding system 30. Bits a0-a19 represent bits of data that will be transmitted or recorded in channel 16. ECC encoder module 12 processes bits a0-a19 to generate ECC parity bits r0-r19. ECC parity bits r0-r19 can be in a contiguous block that is concatenated with data bits a0-a19. Inner encoder module 32 inserts inner-code parity bits 36 of the inner code at predetermined positions among bits a0-a19. The predetermined positions are based on the inner code.
Referring now to FIG. 5, a functional block diagram is shown of a hard disk drive (HDD) 40. HDD 40 can employ the ECC, constrained code, and inner code to read and write encoded data on a rotating magnetic platter 42. The encoded data is stored on platter 42 in a pattern of tracks 44. Magnetic platter 42 and tracks 44 implement channel 16 of FIG. 3. Tracks 44 are divided into a plurality of sectors 46.
Each sector 46 can include servo data that is written at predetermined locations on platter 42. The servo data is used by a hard drive control (HDC) module 48 to determine the position of a read/write (R/W) head 50 with respect to platter 42. HDC module 48 communicates with a motor control module 52 that controls the positions and velocities of platter 42 and R/W head 50. Since the servo data is written at predetermined locations and cannot be moved, it can be challenging for HDC module 48 to anticipate when the encoded data and inner code parity bits 36 will be written to a portion of platter 42 that includes the immovable servo data. This is particularly true when ECC encoder module 12 and constrained encoder module 14 are implemented in HDC module 48, and inner encoder module 32 is implemented in a R/W channel module 54.
A symbol clock cadence module 56 varies a clock frequency relationship between HDC module 48 and R/W channel module 54. Symbol clock cadence module 56 receives information from R/W channel module 54 regarding the positions of inner-code parity bits 36 and receives information from HDC module 48 regarding expected positions of the servo data on platter 42. Based on the information, symbol clock cadence module 56 varies a throughput or cadence relationship between HDC module 48 and R/W channel module 54. Varying the cadence relationship prevents the encoded data and/or inner parity bits from being written to a location on platter 42 that already includes the servo data.
Referring now to FIG. 6, a functional block diagram is shown of pertinent parts of HDC module 48 and R/W channel module 54. ECC encoder module 12 can be implemented in HDC module 48 and can include a Reed-Solomon (RS) ECC encoder module 12A. RS ECC encoder module 12A generates the ECC parity bits. ECC encoder module 12 also includes a RLL encoder module 12B that encodes the ECC parity bits with a RLL code. A multiplexer 12C concatenates the encoded data from constrained encoder module 14 with the RLL-encoded ECC parity bits from RLL encoder module 12B. HDC module 48 can also include ECC decoder module 20 and constrained decoder module 18.
A data diagram 60 shows that the data stream at the output of ECC encoder module 12 includes the encoded data from constrained encoder module 14 and the RLL-encoded ECC parity bits from RLL encoder module 12B. A coding rate of RLL encoder module 12B can be lower than a coding rate of constrained encoder module 14.
R/W channel 54 can include inner encoder module 32 and inner decoder module 34. Inner decoder module 34 can also include a soft-output Viterbi algorithm (SOVA) module 34A that generates soft information based on characteristics of channel 16. Inner decoder module 34 decodes data that it receives from channel 16 based on the soft output.
A second data diagram 62 shows that the RLL coded data is interspersed with inner-code parity bits 36 that are generated by inner encoder module 32. Since inner encoder module 32 generates inner-code parity bits 36 independently of HDC module 48, it is challenging for HDC module 48 to anticipate where inner-code parity bits 36 will be recorded on platter 42 (which is included in channel 16). It is similarly challenging to HDC module 48 to avoid writing to the locations on platter 42 that include the servo data.
Referring now to FIG. 7, a data diagram 70 shows an example pattern of inner-code parity bits 36. Inner encoder module 32 can insert two inner-code parity bits 36 for each twenty bits of encoded data from ECC encoder module 12. It should be appreciated that other numbers of bits may also be used depending on a desired efficiency of data throughput in channel 16.
Referring now to FIG. 8, data diagrams 76 and 78 show an effect of the pattern of inner-code parity bits 36 that is shown in FIG. 7. ECC encoder module 12 outputs the encoded data and RLL-encoded ECC parity bits in blocks of ten bits, which are shown generally at 76. Inner encoder module 32 inserts two inner-code parity bits 36 for every twenty bits of the encoded data that it receives, which is shown generally at 78. The inserted two bits cause the ten-bit blocks of encoded data to become out of phase between HDC module 48 (which includes ECC encoder module 12) and R/W channel module 54 (which includes inner encoder module 32). HDC module 48 therefore needs symbol clock cadence module 56 (shown in FIG. 5) to meter a symbol rate of the bits that are shown at 76 and 78 and thereby avoid writing bits at locations on platter 46 that include the predetermined servo data.